1. Field of the Invention
The invention relates to digital apparatus capable of operating at bit rates in excess of one-half gigabits per second and in particular to apparatus for converting a three level coded signal transmitted at these high bit rates to a conventional binary format.
2. Description of the Prior Art
In high speed data communications, coherent optical paths have been proposed having data transmission rates from a half to tens of gigabits per second. An implementation problem posed by such optical communication channels is that of recovering the data and the clocking, usually as a preliminary to distributing the data to a number of individual channels of lower bandwidth. Such a system is described in U.S. application Ser. No. 688,375, filed Jan. 2, 1985, and entitled MONOLITHICALLY INTEGRATED ELECTRO-OPTICAL MULTIPLEXER/DEMULTIPLEXER (Messrs Fitelson, Wanuga and Williams).
It has been proposed that the optical signal in such channels be self clocking by resort to three level coding. In three level coding, a transition occurs at each clocking interval allowing recovery of the clocking directly by sensing the transitions. The data may be decoded, when a three level coded data stream is employed, to obtain a bit of data in binary format for each clocking interval.
At the high bit rates herein contemplated, monolithically integrated circuit fabrication is essential in view of the great speed required of individual active devices making up the decoder logic and in view of the need for interconnections between logic cells, which can efficiently carry signals at these high frequencies. The logic design, the circuit design of the logic, and the design of individual semiconductor devices within the circuitry must all be compatible with high speed operation. In particular, the maintenance of rigorous timing accuracy throughout all elements of the decoder and through the full variety of operations required of the decoder has presented a challenge to the designer.